Investigation of DC Characteristics in Polysilicon Nanowire Tunneling Field-Effect Transistors
폴리실리콘 나노선기반 터널링 전계효과 트랜지스터의 DC 특성 분석
- 주제(키워드) TFET , Single grain boundary , Threshold voltage , Ambipolar effect
- 발행기관 포항공과대학교 일반대학원
- 지도교수 백창기
- 발행년도 2017
- 학위수여년월 2017. 2
- 학위명 석사
- 학과 및 전공 일반대학원 창의IT융합공학과
- 원문페이지 55
- 실제URI http://www.dcollection.net/handler/postech/000002330199
- 본문언어 한국어
- 저작권 포항공과대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
We simulated polysilicon nanowire tunneling field-effect transistors (poly-Si NW TFETs) for ultra-low power applications. DC characteristics (threshold voltage(Vth), ambipolar effect, on-current(Ion)) of poly-Si NW TFETs were investigated when a single grain boundary (SGB) existed in the channel region. Poly-Si NW TFETs were analyzed using 3-D numerical simulations in terms of different locations and sizes of the SGB. As the SGB was closer to the source/channel junction, longer source-side tunneling path increased Vth but decreased Ion because the captured electrons at the acceptor-like states in the SGB shift conduction band upward at on-state condition. On the other hand, as the SGB was closer to the channel/drain junction, longer drain-side tunneling path decreased ambipolar effect because the captured holes at the donor-like states in the SGB shift valence band downward at reverse-bias condition. In addition, the wider SGBs at the source/channel and the channel/drain junctions induced the longer tunneling path, and increased Vth and decreased Ion and ambipolar effect at on-state and reverse bias conditions, respectively.
more목차
Abstract
Table of Contents
List of Figures
List of Tables
I. Introduction
II. Background
2.1 Operation properties of TFET
2.2 Issues of TFET
III. Investigation of DC Characteristics of poly-Si NW TFETs
3.1 Device structure and simulation models
3.1.1 Device structure
3.1.2 Simulation models
3.2 Simulation result and discussion
3.2.1 Location split of SGB
3.2.2 Width split of SGB
IV. Conclusion
References