DABC-NV: A buffer cache architecture for mobile systems with heterogeneous flash memories
- 주제(키워드) buffer cache , MLC flash memory , NANDflash memory , NVRAM , replacement algorithm
- 관리정보기술 faculty
- 등재 SCIE, SCOPUS
- 발행기관 Institute of Electrical and Electronics Engineers
- 발행년도 2012
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000097645
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/TCE.2012.6414991
초록/요약
Flash memory is widely used in mobile consumer electronics devices due to its good properties such as small size, shock resistance, and low-power consumption. However, the cost of flash memory is still high to accommodate ever-growing mobile applications and multimedia contents. Using MLC (multilevel cell) technologies is an efficient solution to extend the storage capacity, but it degrades the performance of flash memory significantly compared to the original storage based on SLC (single-level cell) technologies. To bridge the characteristics of the two technologies, this paper presents a new buffer cache management scheme that uses both MLC and SLC together and considers their heterogeneous characteristics. By allocating cache space based on the characteristics of each storage media as well as I/O operation types and reference history of buffered blocks, the proposed scheme improves the I/O performance of mobile systems by 24% on average and up to 180% compared to the CLOCK algorithm. Moreover, it guarantees high reliability of file data by adopting recently emerging non-volatile RAMs in a certain portion of the buffer cache. © 2011 IEEE.
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