A 3.125-to-22-Gb/s multi-rate clock and data recovery using voltage-regulated active filter
- 주제(키워드) CDR , multi-rate , PVT variation , ring VCO , voltage-regulated active filter
- 등재 SCIE, SCOPUS
- 발행기관 IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- 발행년도 2014
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000114346
- 본문언어 영어
- Published As http://dx.doi.org/10.1587/elex.11.20140953
초록/요약
This letter presents a multi-rate clock and data recovery circuit realized in a standard 65-nm CMOS technology, which operates from 3.125 Gb/s to 22 Gb/s. In order to cover the wide frequency range, a modified four- stage differential ring VCO is exploited, which provides not only the fast tracking ability from its coarse tuning, but also the precise tra cking from its fine tuning. Also, a voltage-regulated active filter is employed to reduce the ripples of the VCO control voltages. It helps to fasten the lock-in time of the proposed CDR circuit and improve the jitter characteristics against PVT variations. Measurements reveal that the CDR chip demonstrates very wide capture range of 3.125 similar to 22 Gb/ s, 3.3 ps(,rms) data jitter at 20 Gb/s, and 112-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 0.12 mm(2) only.
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