A 6.6 mW, -94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS
- 주제(키워드) CMOS , frequency synthesizer , PLL , ring VCO , tuning range
- 등재 SCOPUS
- 발행기관 Institute of Electrical and Electronics Engineers Inc.
- 발행년도 2015
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000131138
- ISBN 9781467393089
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/ISOCC.2015.7401734
초록/요약
This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0∼4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0∼4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2. © 2015 IEEE.
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