Analysis of Memory Access Latency Considering Page Faults and TLB Misses in NVM Storage
- 주제(키워드) Memory access , NVM , page size , TLB , page fault
- 주제(기타) Engineering, Electrical & Electronic; Physics, Applied
- 설명문(일반) [Park, Yunjoo; Bahn, Hyokyung] Ewha Womans Univ, Dept Comp Engn, Seoul, South Korea
- 관리정보기술 faculty
- 등재 SCIE, SCOPUS, KCI등재
- 발행기관 IEEK PUBLICATION CENTER
- 발행년도 2018
- URI http://www.dcollection.net/handler/ewha/000000151534
- 본문언어 영어
- Published As http://dx.doi.org/10.5573/JSTS.2018.18.1.014
초록/요약
As high performance NVM storage emerges, memory system configurations optimized for HDD should be revisited. This paper explores the performance of memory systems that use NVM as a storage device and discusses how such systems can be managed efficiently. Specifically, we analyze the memory access time separately for address translation latency and data access latency as the page size, read-ahead, and storage performances are varied. As the page fault cost becomes small under NVM storage, we observe that the bottleneck of memory systems can be shifted to address translation. We show that determining an appropriate page size can improve the address translation latency without increasing data access latency. We also show that turning off the read-ahead option is helpful in reducing data access latency. We expect that our new architecture with appropriate configurations will be helpful in the design of emerging memory systems.
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