A CMOS symmetric self-biased voltage reference
- 주제(키워드) CMOS , Constant-g(m) , Modified cascode , PVT variation , Self-biased , Voltage reference
- 주제(기타) Engineering, Electrical & Electronic; Nanoscience & Nanotechnology
- 설명문(일반) [Park, Minseon; Park, Sung Min] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul, South Korea
- 등재 SCIE, SCOPUS
- 발행기관 ELSEVIER SCI LTD
- 발행년도 2018
- URI http://www.dcollection.net/handler/ewha/000000156082
- 본문언어 영어
- Published As http://dx.doi.org/10.1016/j.mejo.2018.08.002
초록/요약
This paper presents a novel CMOS voltage reference circuit named symmetric self-biased voltage reference (SSVR), which enables not only to discard the voltage headroom issue of a conventional constant-g(m) current source and the inevitable need of an extra bias in a modified constant-g(m), current source, but also to maintain stable bias voltages with strong tolerance against significant variations of power supply and temperature. Test chips of the SSVR were implemented by using a 0.11-mu m CMOS process. Measured results demonstrate that the symmetric configuration of the proposed SSVR helps to achieve constant voltage references against the V-DD variation from 0.7 to 1.2V and the temperature variation from -15 degrees C to 125 degrees C. The fabricated chip consumes constant 18.5 mu A currents for 0.7 similar to 1.0-V supply voltages and its core occupies the area of 0.04 x 0.047 mm(2).
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