A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency
- 주제(키워드) One-transistor DRAM , SiGe quantum well , band-to-band tunneling , DRAM retention , low-power operation
- 주제(기타) Engineering, Electrical & Electronic
- 설명문(일반) [Yu, Eunseon; Cho, Seongjae] Gachon Univ, Dept Elect Engn, Seongnam 13120, South Korea; [Shin, Hyungsoon] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul 03760, South Korea; [Park, Byung-Gook] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea
- 등재 SCIE, SCOPUS
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2019
- URI http://www.dcollection.net/handler/ewha/000000159701
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/LED.2019.2902334
초록/요약
In this letter, a one-transistor (1T) dynamic random-access memory (DRAM) with SiGe quantum well (QW) is proposed, and its performance is validated through the technology computer-aided design (TCAD) simulation. At the write operation, band-to-band tunneling is used and 1 V or lower programming voltage is realized by inserting the SiGe QW beside the drain. This QW also functions as the storage node, which enhances not only the current sensing margin but also the retention time (tau(ret)) compared with those of all-Si device. At an extremely scaled cell size and sub-10-ns write/erase operations, the proposed device shows 0.2-s-long tau(ret) and current ratio > 10(4). It has been verified that a single cycle of 1T DRAM operations consumes only 93.8 fJ.
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