Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect
- 주제(키워드) poly-Si , 1T DRAM , grain boundary , sensing margin , retention , embedded DRAM
- 주제(기타) Engineering, Electrical & Electronic
- 설명문(일반) [Seo, Jae Hwa; Lee, Jong-Ho] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea; [Yoon, Young Jun; Kang, In Man] Kyungpook Natl Univ, Sch Elect Engn, Daegu 41566, South Korea; [Yu, Eunseon; Cho, Seongjae] Gachon Univ, Dept IT Convergence Engn, Gyeonggi Do 13120, South Korea; [Sun, Wookyung; Shin, Hyungsoon] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul 03760, South Korea; [Cho, Seongjae] Gachon Univ, Dept Elect Engn, Gyeonggi Do 13120, South Korea
- 등재 SCIE, SCOPUS
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2019
- URI http://www.dcollection.net/handler/ewha/000000159702
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/LED.2019.2901003
초록/요약
A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped n(+) source and drain junctions, nearly intrinsic n-channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (T-body). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2 mu A/mu m and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.
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