A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
- 주제(키워드) Asymmetric transformers , CMOS , mirrored cascode (MC) , single to differential , transimpedance amplifier (TIA)
- 주제(기타) Engineering, Electrical & Electronic
- 설명문(일반) [Kim, Sang Gyun; Eo, Yun Seong] Kwangwoon Univ, Dept Elect Engn, Seoul 01897, South Korea; [Hong, Chaerin; Kim, Jihoon; Park, Sung Min] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul 03760, South Korea
- 등재 SCIE, SCOPUS
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2019
- URI http://www.dcollection.net/handler/ewha/000000159961
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/JSSC.2018.2886323
초록/요약
This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i. e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB Omega transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, 19.8-pA/root Hz average noise current spectral density, +/- 10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215-1 pseudo random binary sequence (PRBS) were measured with the input currents of 100-1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.
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