Tight Evaluation of Real-Time Task Schedulability for Processor's DVS and Nonvolatile Memory Allocation
- 주제(키워드) real-time system , dynamic voltage scaling , task placement , low-power technique , nonvolatile memory
- 주제(기타) Nanoscience & Nanotechnology
- 주제(기타) Instruments & Instrumentation
- 관리정보기술 faculty
- 등재 SCIE, SCOPUS
- OA유형 Green Published, Green Submitted, gold
- 발행기관 MDPI
- 발행년도 2019
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000161222
- 본문언어 영어
- Published As http://dx.doi.org/10.3390/mi10060371
- PubMed https://pubmed.ncbi.nlm.nih.gov/31163692
초록/요약
A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task's memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor's voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18-88%.
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