Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode
- 주제(키워드) capacitorless DRAM , grain boundary , poly-Si 1T-DRAM , junctionless (JL) transistor
- 주제(기타) Engineering, Electrical & Electronic
- 주제(기타) Materials Science, Multidisciplinary
- 주제(기타) Physics, Condensed Matter
- 등재 SCIE, SCOPUS
- 발행기관 IOP PUBLISHING LTD
- 발행년도 2019
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000161509
- 본문언어 영어
- Published As http://dx.doi.org/10.1088/1361-6641/ab3a07
초록/요약
Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor's body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.
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