High-Throughput Non-Binary LDPC Decoder Based on Aggressive Overlap Scheduling
- 주제(키워드) NB-LDPC codes , overlap schedule , low latency check node processing , memory reuse technique
- 주제(기타) Engineering, Electrical & Electronic
- 등재 SCIE, SCOPUS
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2017
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000162126
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/TCSI.2017.2677518
초록/요약
Non-binary LDPC (NB-LDPC) codes offer better error correcting performance than their binary counterparts. However, to achieve excellent performance, decoding complexity and large memory are required, which makes it difficult to implement the high-throughput decoder. This paper presents a fully overlapped NB-LDPC decoder using three proposed techniques to improve throughput performance. First, an early bubble check is presented to reduce the initialization latency of the check node processing (CNP). Second, the CNP and variable node processing (VNP) are overlapped with the proposed backward memory scan method to hide the CNP latency within the VNP. Finally, we propose a redundant memory reuse technique to further decrease the latency of a single decoding iteration. We implemented the high-throughput decoder for (160, 80) regular (2, 4) NB-LDPC code over GF (64). The iteration latency was decreased by up to 57.5% with our three proposed methods. The proposed decoder achieved a throughput of 2.22 Gb/s at a 625-MHz frequency with 2.96-M gates in a 65-nm CMOS process. The proposed decoder showed outstanding area efficiency compared with the state-of-the-art decoders.
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