Optimization considerations for short channel poly-Si 1T-DRAM
- 주제(키워드) 1T-DRAM , Capacitorless one-transistor dynamic random-access memory , Grain boundary , Polysilicon , Trapped electron , Trapped hole
- 등재 SCIE, SCOPUS
- OA유형 gold, Green Published
- 발행기관 MDPI AG
- 발행년도 2020
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000169428
- 본문언어 영어
- Published As https://dx.doi.org/10.3390/electronics9061051
- 저작권 이화여자대학교 논문은 저작권에 의해 보호받습니다.
초록/요약
Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.
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