Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM
- 주제(키워드) capacitorless one-transistor dynamic random-access memory , 1T-DRAM , polysilicon , grain boundary , lateral grain boundary (GB) , GB location
- 주제(기타) Nanoscience & Nanotechnology
- 주제(기타) Instruments & Instrumentation
- 설명문(일반) [Yoo, Songyi; Shin, Hyungsoon] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul 03760, South Korea; [Yoo, Songyi; Shin, Hyungsoon] Ewha Womans Univ, Smart Factory Multidisciplinary Program, Seoul 03760, South Korea; [Sun, Wookyung] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 08826, South Korea
- 등재 SCIE, SCOPUS
- OA유형 Green Published, gold
- 발행기관 MDPI
- 발행년도 2020
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000175143
- 본문언어 영어
- Published As http://dx.doi.org/10.3390/mi11110952
- PubMed https://pubmed.ncbi.nlm.nih.gov/33105643
초록/요약
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). A poly-Si 1T-DRAM cell operates as a memory by utilizing the charge trapped at the grain boundaries (GBs) of its poly-Si body; vertical GBs are formed randomly during fabrication. This paper describes technology computer aided design (TCAD) device simulations performed to investigate the sensing margin and retention time of poly-Si 1T-DRAM as a function of its lateral GB location. The results show that the memory's operating mechanism changes with the GB's lateral location because of a corresponding change in the number of trapped electrons or holes. We determined the optimum lateral GB location for the best memory performance by considering both the sensing margin and retention time. We also performed simulations to analyze the effect of a lateral GB on the operation of a poly-Si 1T-DRAM that has a vertical GB. The memory performance of devices without a lateral GB significantly deteriorates when a vertical GB is located near the source or drain junction, while devices with a lateral GB have little change in memory characteristics with different vertical GB locations. This means that poly-Si 1T-DRAM devices with a lateral GB can operate reliably without any memory performance degradation from randomly determined vertical GB locations.
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