Characterization of Android Memory References and Implication to Hybrid Memory Management
- 주제(키워드) Nonvolatile memory , Random access memory , Memory management , Social networking (online) , Performance evaluation , Focusing , Browsers , Android , smartphone , application , memory reference , NVM , write operation , hybrid memory
- 주제(기타) Computer Science, Information Systems
- 주제(기타) Engineering, Electrical & Electronic
- 주제(기타) Telecommunications
- 설명문(일반) [Lee, Soyoon; Bahn, Hyokyung] Ewha Womans Univ, Dept Comp Engn, Seoul 120750, South Korea
- 관리정보기술 faculty
- 등재 SCIE, SCOPUS
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2021
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000181573
- 본문언어 영어
- Published As http://dx.doi.org/10.1109/ACCESS.2021.3074179
초록/요약
In this article, we analyze Android applications' memory reference behaviors, and observe that smartphone memory accesses are different from traditional computer systems with respect to the following five aspects: 1) A limited number of hot pages account for a majority of memory writes, and these hot pages have similar logical addresses regardless of application types; 2) The identities of these hot pages are shared library, linker, and stack regions; 3) The memory access behaviors of hot pages do not change significantly as time progresses even after applications finish their launching; 4) The skewness of memory write accesses in Android is extremely stronger than that of desktop systems; 5) In predicting re-reference likelihood of hot pages, temporal locality is better than reference frequency. Based on these observations, we present a new smartphone memory management scheme for DRAM-NVM hybrid memory. Adopting NVM is effective in power-saving of smartphones, but NVM has weaknesses in write operations. Thus, we aim to identify write-intensive pages and place them on DRAM. Unlike previous studies, we prevent migration of pages between DRAM and NVM, which eliminates unnecessary NVM write traffic that accounts for 32-42% of total write traffic. By judiciously managing the admission of hot pages in DRAM, our scheme reduces the write traffic to NVM by 42% on average without performance degradations.
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