Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective
- 주제(키워드) Algorithm-hardware co-design , Brain-computer interface (BCI) , Deep learning accelerator , Domain-specific architecture , Linear algebra accelerator
- 등재 SCIE, SCOPUS
- 발행기관 Institute of Electrical and Electronics Engineers Inc.
- 발행년도 2022
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000193296
- 본문언어 영어
- Published As https://doi.org/10.1109/TCSII.2022.3177616
초록/요약
Brain-computer interface (BCI), a communication technology between brain and computer developed for a long time since the 1970s, can be incorporated into wearable devices by developing powerful signal processing algorithms and semiconductor technologies. For a satisfactory user experience based on BCI, high information transfer rate and low power consumption should be considered together without losing accuracy. Although many existing BCI algorithms have been mainly focused solely on the accuracy, their deployment on wearable devices is not straightforward due to the limited hardware resources and computational capabilities. This tutorial summarizes recent advances in wearable BCI algorithms and hardware implementations from an algorithm-hardware co-design perspective and discusses future directions. © 2004-2012 IEEE.
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