TEA-RC: Thread Context-Aware Register Cache for GPUs
- 주제(키워드) Registers , Instruction sets , Graphics processing units , Kernel , Random access memory , Nonvolatile memory , Message systems , Graphics processing units , register file , register cache , volatile memory , non-volatile memory , hybrid register file , hierarchical register file
- 주제(기타) Computer Science, Information Systems
- 주제(기타) Engineering, Electrical & Electronic
- 주제(기타) Telecommunications
- 설명문(일반) [Jeong, Ipoom; Ro, Won Woo] Yonsei Univ, Sch Elect & Elect Engn, Seoul 03722, South Korea; [Oh, Yunho] Korea Univ, Sch Elect Engn, Seoul 02841, South Korea; [Yoon, Myung Kuk] Ewha Womans Univ, Dept Comp Sci & Engn, Seoul 03760, South Korea
- 관리정보기술 faculty
- 등재 SCIE, SCOPUS
- OA유형 gold
- 발행기관 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- 발행년도 2022
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000194551
- 본문언어 영어
- Published As https://doi.org/10.1109/ACCESS.2022.3196149
초록/요약
Graphics processing units (GPUs) achieve high throughput by exploiting a high degree of thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register file to store the context of all threads, consuming around 20% of total GPU energy. Several previous studies have attempted to minimize the energy consumption of the register file by implementing an emerging non-volatile memory (NVM), leveraging its higher density and lower leakage power over SRAMs. To amortize the cost of long access latency of NVM, prior work adopts a hierarchical register file consisting of an SRAM-based register cache and NVM-based registers where the register cache works as a write buffer. To get the register cache index, they use the partially selected bits of warp ID and register ID. This work observes that such an index calculation causes three types of contentions leading to the underutilization of the register cache: inter-warp, intra-warp, and false contentions. To minimize such contentions, this paper proposes a thread context-aware register cache (TEA-RC) in GPUs. In TEA-RC, the cache index is calculated considering the high correlation between the number of scheduled threads and the register usage of threads. The proposed design shows 28.5% higher performance and 9.1 percentage point lower energy consumption over the conventional register cache that concatenates three bits of warp ID and five bits of register ID to compute the cache index.
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