A 208-MHz, 0.75-mW Self-Calibrated Reference Frequency Quadrupler for a 2-GHz Fractional-N Ring-PLL in 4-nm FinFET CMOS
- 주제(키워드) Clock multiplier , delay control , duty-cycle correction (DCC) , phase-locked loop (PLL) , reference frequency doubler , reference frequency quadrupler
- 등재 SCIE, SCOPUS
- 발행기관 Institute of Electrical and Electronics Engineers Inc.
- 발행년도 2023
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000211429
- 본문언어 영어
- Published As https://doi.org/10.1109/TCSII.2022.3217756
초록/요약
This brief presents a 208-MHz, 0.75-mW self-calibrated reference frequency quadrupler (RFQ), which provides a 4x higher reference clock with minimal deterministic frequency error. The digital-assisted calibration technique is exploited to compensate wide range of frequency and duty cycle errors and to reduce the noise degradation of analog calibration loop. Also, instead of utilizing a duty cycle corrector for 2x clock, reusing a delay cell reduces the power consumption by 50%. The fractional-N ring-PLL with the proposed RFQ was implemented in a 4nm FinFET CMOS process. The active area of the RFQ is 0.0175mm2 while the whole PLL occupies the area of 0.109mm2. By using the RFQ, the measured RMS-jitter of the PLL is definitely improved from 6.6ps to 3.35ps at 1.92GHz output frequency. © 2004-2012 IEEE.
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