Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction
- 주제(키워드) Dual workfunction , junction underlap , line tunneling field-effect transistor (LTFET) , low-power operation , TCAD device simulation
- 등재 SCIE, SCOPUS, KCI등재
- 발행기관 Institute of Electronics Engineers of Korea
- 발행년도 2023
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000211799
- 본문언어 영어
- Published As https://doi.org/10.5573/JSTS.2023.23.4.207
초록/요약
In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. © 2023, Institute of Electronics Engineers of Korea. All rights reserved.
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