An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network
- 주제(기타) Engineering, Electrical & Electronic
- 설명문(일반) [Shah, Arati Kumari; Udaya Mohanan, Kannan; Cho, Eou-Sik] Gachon Univ, Dept Elect Engn, Seongnam 13120, Gyeonggi, South Korea; [Shah, Arati Kumari; Park, Jisun; Shin, Hyungsoon; Cho, Seongjae] Ewha Womans Univ, Dept Elect & Elect Engn, Seoul 03760, South Korea
- 등재 SCIE, SCOPUS
- OA유형 Gold Open Access
- 발행기관 WILEY-HINDAWI
- 발행년도 2023
- 총서유형 Journal
- URI http://www.dcollection.net/handler/ewha/000000213331
- 본문언어 영어
- Published As https://doi.org/10.1049/2023/1052063
초록/요약
Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-mu m Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 mu W per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.
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