Validating Consistency between a Feature Model and its Implementation
- 발행기관 Pohang University of Science and Technology
- 지도교수 Kyo Chul Kang
- 발행년도 2012
- 학위수여년월 2012. 8
- 학위명 석사
- 학과 및 전공 일반대학원 정보전자융합공학부
- 원문페이지 70
- 실제URI http://www.dcollection.net/handler/postech/000001388635
- 본문언어 영어
초록/요약
Consistency across different lifecycle artifacts is an important issue in software engineering. In Software Product Line Engineering (SPLE), validating consistency becomes even more complicated because product line assets have embedded variabilities. Commonality and variability (C&V) of a software product line (SPL) are usually captured using a feature model. Then, they are embedded into an implementation (i.e., asset code) using various techniques including preprocessor directives. However, the product line asset code often evolves without properly updating other lifecycle artifacts including the variability model, and verification of the consistency of C&V across different product line assets is a major challenge. In this thesis, I propose an approach to validating the consistency between C&V expressed in a feature model and C&V embedded in an implementation. With this approach, product line engineers can have a method for maintaining consistency across of SPL assets systematically. This method has been applied to the flash memory product line at Samsung Electronics Co. Ltd. and improvements have been made over the years based on the feedback.
more목차
Contents 2
List of Figures 4
List of Tables 5
1. Introduction 6
2. Background 11
2.1. Features and Feature Models 11
2.2. Embedding Features into Implementation 12
3. Concepts and Methods 14
3.1. Reverse engineering Phase 14
3.1.1. Extracting Variability Information 16
3.1.2. Extracting a Feature Model 23
3.2. Validation Phase 29
3.2.1. Semantic Consistency 29
3.2.2. Syntactic Consistency 30
4. A Case Study: MicroC/OS-II 33
4.1. Support Tools 34
4.1.1. Reverse Engineering Feature Model 34
4.1.2. Feature Mapping 34
4.1.3. Refactoring Feature Model 34
4.1.4. FeatureIDE: Configuration Comparison 35
4.1.5. Structural Comparison of Feature Model 35
4.1.6. Understand 2.0: Reverse Engineering Structural Dependencies 35
4.2. Analysis Result 36
4.2.1. MicroC/OS-II Overview 36
4.2.2. Memory Management 37
4.2.3. Task Management 38
4.2.4. Event Flag Management 40
4.3. Summary… 41
5. Related Work 43
6. Discussion 45
6.1. Conclusion.. 45
6.2. Summary of Contribution 48
6.3. Limitation and Future Research 49
Appendix A: Feature Mapping 50
Appendix B: Support tools tutorials 52
A. Reverse Engineering Feature Model 52
B. Feature Mapping 55
C. Refactoring Feature Model 56
D. FeatureIDE: Configuration Comparison 58
E. Structural Comparison of Feature Models 59
References 61